Three-dimensional or 3D integration comprises stacking electronic components by superposing dies and/or wafers on one another and by creating vertical electric connections between these components by using interconnection pillars and/or vias crossing the different die or wafer layers.
As illustrated in FIGS. 1 and 2, dies are generally series-manufactured on semi-conductor wafers based on silicon or the like, which are then sawn. More specifically, functional areas 15, 25 necessary to the implementation of the dedicated functions of dies 1, 2, are etched in a semiconductor bulk 10, 20 of the wafer. Functional areas 15, 25 are further connected to different metal interconnection levels 13, 23 formed within an insulating layer 11, 21 typically based on oxide or the like, formed on the upper surface of the wafer. Such different metal interconnection levels 13, 23 especially enable to transfer electric connections from functional areas 15, 25 to upper surface 110, 210 (or front surface) of insulating layer 11, 21 in expectation of a connection with other dies. The wafer can then be sawn to separate the different chips thus obtained.
According to a practice illustrated in FIGS. 1 to 4, the die stack may be of face-to-face type, that is, with front surfaces 110, 210 of two dies 1, 2 being arranged in front of each other. In this specific case, to form the vertical electric connection between a first and a second die 1, 2, it is current to provide, for each of dies 1, 2, interconnection pillars 14, 24. Each pillar 14, 24 extends from a conductive area or pad 130, 230 of front surface 110, 210 of die 1, 2 and protrudes from front surface 110, 210 of die 1, 2.
Conductive areas 130, 230, typically based on copper, aluminum, or the like, generally form what is called the last metal interconnection level of metal levels 13, 23 of the oxide layer of die 1, 2. Conductive areas 130, 230 are especially used as lands for the growth of interconnection pillars 14, 24. Further, each pillar 14, 24 may be topped with a dome 140 based on a tin silver alloy (Sn/Ag) intended to ease the soldering to another interconnection pillar or another connection area.
To vertically connect the two dies 1, 2, the free end of one of interconnection pillars 14 of first die 1 should thus be placed in contact with the free end of one of interconnection pillars 24 of second die 2, and an annealing should be performed to melt dome 140 and merge the two pillars 14, 24. The space left between front surfaces 110, 210 of the two dies 1, 2 may then be filled by deposition of a polymer resin 3 of epoxy type or the like, commonly called underfill. Finally, an encapsulation resin 4 is deposited to fully cover one of the dies, and especially first die 1.
Further, as illustrated in FIGS. 2 and 4, it is also possible to provide metallized interconnection holes 26 in second die 2. Such metallized interconnection holes 26, also called “vias” or TSVs (“Through Silicon Vias”), are electrically connected to metal interconnection levels 23 of second die 2 and open out on lower surface 211 (or rear surface) of this second die 2.
A metal redistribution layer 27 (or RDL) is generally deposited on rear surface 211 of the second die 2 in the form of metal tracks. Redistribution layer 27 is in contact with vias 26, and is used as a support for the growth of conductor pads 28 protruding from rear surface 211 of second die 2. Pads 28 especially create an electric connection with a support for example having different connection pitches, or simply enable to have directly accessible electrodes.